Ok. How do you get make to conditionally include a file, based on the calling arguments? I’m not sure that this can be done, but I’d love to be proven otherwise.
I have a make file that builds a third party sub-project if it hasn’t been built. It does this by including the sub-project’s make file. The problem is that if the make file doesn’t exist, a rule gets triggered to create it, which is a laborious process involving untarring a huge tarball and running through a sort of autobuild. The issue is that any target will trigger this, because of the “include” rule. This looks sort of like this:
… blah blah make rulesSo, if you “make clean”, and the project is already clean, the include triggers the create makefile rule, which then takes two or three minutes to create the makefile… so that it can be immediately deleted.
…. blah blah other clean tasks
What I can’t figure out is how to get make to conditionally include the file, or conditionally execute the make file creation rule, such that if “clean” is being resolved, it doesn’t include the make file. I suspect that it has to do with some combination of $^ and the if clause, but I’m not yet sure if those auto-variables are set at the top level. Anyway, I’m still exploring.